1. Field of the Invention
The present invention relates to semiconductor memories, particularly to a semiconductor memory such as a synchronous dynamic random-access memory (to be referred to as SDRAM hereinafter) having a cell array including banks and capable of independently controlling these banks.
2. Description of the Related Art
In a semiconductor memory such as SDRAM, one chip is divided into banks, which are controlled independently of each other. FIG. 1 shows a timing chart when four banks (Bank0 to Bank3) are individually controlled.
In this timing chart of FIG. 1, the state of a block in each bank is always an active or pre-charge state, and these active and pre-charge states are alternately switched. In the active state, a predetermined block in a bank is activated to enable data read and write. In the pre-charge state, a block in an activated bank is restored to the state before being activated.
When a bank is in the active state, a specific word line in the bank rises to enable data write or read to a particular memory cell connected to this word line. In the pre-charge state, no word line rises, so neither data write nor read to a memory cell in the bank is possible.
FIG. 1 shows a case in which the pre-charge and active states are switched most frequently when write and read operations to a memory are performed. A block in each bank is set in the active state when receiving active commands (ACT0 to ACT3) and in the pre-charge state when receiving pre-charge commands (PRE0 to PRE3).
Operations of each bank are as follows. Operations performed in the active state are: (A1) xe2x80x9cblock selectionxe2x80x9d for selecting a sense amplifier column to be activated; (A2) xe2x80x9cword line selectionxe2x80x9d for selecting a word line in a block; and (A3) xe2x80x9csense amplifier activationxe2x80x9d for amplifying read data. Operations performed in the pre-charge state are: (P1) xe2x80x9cword line resetxe2x80x9d for setting a word line in a non-selected state; and (P2) xe2x80x9cblock selection releasexe2x80x9d for setting a sense amplifier in a non-active state and resetting a bit line to a standby state.
A semiconductor memory having four banks can receive each command in a cycle shown in FIG. 1. In a period indicated by {circle around (1)} in FIG. 1, while an operation for switching bank 0 (Bank0) from the pre-charge state to the active state is performed, a pre-charge operation of bank 2 (Bank2) is started, and the active state of bank 3 (Bank3) and the pre-charge state of bank 1 (Bank1) are maintained. In a period indicated by {circle around (2)}, while a pre-charge operation of bank 3 (Bank3) is performed, an active operation of bank 2 (Bank2) is started, and the active states of bank 0 (Bank0) and bank 1 (Bank1) are maintained.
In SDRAM as described above, while the present state of a bank is maintained, a desired block in another bank can be switched to the active state, and a block in still another bank can be switched to the pre-charge state. That is, the banks can be operated and controlled independently of each other.
To this end, circuits such as sense amplifiers and sub-word drivers arranged in a cross portion, called an SS-Cross portion, between a sense amplifier group and a sub-word decoder group and various circuits for controlling these circuits must be so designed as to be able to control these banks independently.
FIG. 2 is a block diagram showing the arrangement of a cell array block of SDRAM for performing a four-bank operation. FIGS. 3A and 3B are schematic views showing details of the interior of the cell array shown in FIG. 2. The arrangement of SDRAM for performing a four-bank operation will be briefly described below with reference to FIGS. 2, 3A, and 3B. Banks (Bank0 to Bank3) 50 to 53 are provided with word drivers (wd) 54 to 57 as power generators for independently controlling these banks and setting a word line of a desired block in the active state. These word drivers 54 to 57 supply a main WD select signal (mwd) to the adjacent banks 50 to 53. The banks 50 to 53 are also provided with main word decoders (mwdec) 58 to 61. These main word decoders 58 to 61 are connected to main select lines (mwl).
A word line is selected as follows in each of these banks 50 to 53. That is, in accordance with an input row address, the main word decoders 58 to 61 select a desired main select line (mwl). Also, a sub-word decoder (swdec in FIGS. 3A and 3B) driven on the basis of an output main WD select signal (mwd) from the word drivers 54 to 57 selects a desired one of sub-select lines (swl), which belongs to the selected main select line (mwl). Additionally, by selecting a bit line (not shown) in accordance with an input column address, a memory cell at the intersection of the word line and the bit line is selected.
FIG. 3A is a view showing, in an enlarged scale, the internal arrangement of one bank (e.g., Bank0) in the SDRAM shown in FIG. 2. FIG. 3B is a view showing, in a further enlarged scale, a sub-WD signal generator (swdgen) 64 and a sub-word decoder (swdec) 65 connected to this sub-WD signal generator 64 arranged in a cross portion (SS-Cross portion) between a sub-word decoder group (swdecs) 62 and a sense amplifier group (senseAmps) 63 shown in FIG. 3A.
The bank is divided into blocks (four blocks as indicated by the dotted lines in mwdec shown in FIG. 2) along the word line direction. As shown in FIG. 3A, in each block cell array units are formed with sub-word decoder groups 62 and sense amplifier groups 63 perpendicular to each other. Sub-select lines (swl) run from the opposing sub-word decoder groups 62 in an interdigitated pattern. The sense amplifier groups 63 have a function of amplifying an output from a bit line (not shown) running in a direction perpendicular to the sub-select lines (swl). On these sense amplifier groups 63, block signal lines for transmitting block select signals (blk0, blk1, . . .) run in the direction that the sense amplifier groups 63 run.
The sub-WD signal generator 64 shown in FIG. 3B includes an OR gate 64a for performing OR operation of select signals (blk0 and blk1) of adjacent blocks, a NAND gate 64b for performing NAND operation of the output from the OR gate 64a and the main WD select signal (mwd) from the word driver 54, and an inverter 64c for inverting the output from the NAND gate 64b. Complementary signals at the input and output of this inverter 64c are sub-WD select signals (swdz and swdx).
Each of these complementary sub-WD select signals (swdz and swdx) generated by the sub-WD signal generator 64 are input to sub-word decoders 65 connected to this sub-WD signal generator 64. Of these sub-word decoders 65, a sub-word decoder 65 connected to a main select line (mwl) selected by the main word decoder 58 activates a sub-select line (swl). Consequently, a desired memory cell is selected, and data write or read is performed.
FIG. 4 is a timing chart showing signals for controlling the bank 50 (Bank0) and the bank 51 (Bank1). Major ones of these signals shown in FIG. 4 will be described below. When the bank 50 accepts the active command (ACT0), a signal bras0z rises. This signal bras0z indicates whether the bank is in the active state or the pre-charge state. During a period in which the corresponding bank is in the active state, the signal bras0z maintains xe2x80x9cHxe2x80x9d. Upon receiving this xe2x80x9cHxe2x80x9d status signal bras0z, a block select signal (blkz) of a block to which a memory cell to be selected belongs, rises.
Also, when receiving the xe2x80x9cHxe2x80x9d status signal bras0z, a main WD select signal (swl) selected in accordance with a row address rises. Additionally, the sub-WD signal generator 64 activates the sub-WD select signals (swdz and swdx) by logically operating the xe2x80x9cHxe2x80x9d main WD select signal (mwd) and the block select signal (blkz).
A main select line (mwl) falls to xe2x80x9cLxe2x80x9d when selected by the main word decoder 58 in accordance with a row address. The signal of this main select line (mwl) that was fallen to xe2x80x9cLxe2x80x9d upon being selected and the activated sub-WD select signals (swdz and swdx) described above activate a sub-select line (swl) of a memory cell to be selected by the corresponding sub-word decoder 65. After that, write or read to the memory cell is performed via a bit line corresponding to the memory cell.
In the above related art, however, as shown in FIG. 2, independently to control the banks 50 to 53 the word drivers 58 to 61 must be provided in one-to-one correspondence with these banks 50 to 53. That is, circuits having the same function exist in one-to-one correspondence with these banks 50 to 53. This increases the area occupied by the layer of transistors corresponding to the word drivers 58 to 61. Additionally, control lines for the same system are ran to these banks 50 to 53 to increase the area of the wiring layer. This results in the problem of an increased chip area.
Also, the presence of circuits having the same function increases the current driving load, resulting in an increased consumption current. Furthermore, the increase in the driving load decreases the driving speed.
The present invention has been made in consideration of the above situation, and aims to be able to reduce, in a semiconductor memory capable of independently controlling banks, the chip size by minimizing the area of a circuit for controlling each bank, and to reduce the consumption current by reducing the load of a current flowing in the control circuit.
A semiconductor memory according to the present invention comprises a plurality of banks, each of which includes memory cells, and a word line drive circuit selecting one of word lines in the banks in response to first and second select signals produced in accordance with an address. In the semiconductor memory, the first select signal is a pulse signal, and a state of the second select signal which has changed in response to a state change of the first select signal is maintained for a predetermined time in a latch circuit.
Preferably, a first circuit shared by the banks supplies the first select signal to each bank.
Preferably, the first circuit is disposed in substantially the center of the whole region where the banks are arranged.
Preferably, a latch circuit is set in an active state by application of the pulse signal, and maintains the active state until an initiation of a pre-charge operation in the banks.
Preferably, the latch circuit is formed in a second circuit for generating the second select signal.
Preferably, the latch circuit is formed in a second circuit for generating the second select signal, at the corner of a sense amplifier for driving a bit line connected to the memory cells and a word decoder for activating the desired word line in response to the second select signal.
Since the present invention comprises the above technical means, each pulse of the first select signal generated is supplied to the banks. Accordingly, the second select signals of these banks are controlled by one first select signal. Additionally, the state of the second select signals which changes in accordance with the pulse supplied to each bank is maintained for a predetermined time in the bank. Hence, even after a pulse of the first select signal rises, the bank is kept activated, so data can be read from and written in these banks independently of each other.
In the present invention, the first select signal is a pulse signal, and the state of the second select signals which has changed in accordance with the first select signal is maintained for a predetermined time. This permits a circuit for generating the first select signal to be shared by banks. Therefore, it is possible to reduce the chip area of the semiconductor memory and reduce the consumption current.